/*
 * ECU_SBC4500.h
 *
 *  Created on: 2018年12月17日
 *      Author: 40786
 */

#ifndef ECU_SBC4500_H_
#define ECU_SBC4500_H_

uint16_t SBC4500_WD_Refresh(void);
uint16_t SBC4500_Go_Sleep(void);
uint16_t SBC4500_Read_Command(u8 Address);
void SBC4500_Init(void);
uint16_t SBC4500_Start_RTC(void);
uint32_t SBC4500_Read_RTC(void);
void SBC4500_OFFPOWER(void);
uint16_t SBC4500_Release_FS0B(void);
uint16 SPI0_Writedata(uint16 data);
uint16_t SBC4500_Write_data(u8 Address , u8 Command,bool secureFlag);
uint16_t SBC4500_Read_data(u8 Address);
uint16_t SBC4500_Release_FSxB(void);
uint16_t SBC4500_Clear_DiagFlag(void);
/*--------------------------Function On or OFf----------------------------*/
#ifndef ON
#define ON 1
#endif

#ifndef OFF
#define OFF 0
#endif

#define  Fail_Safe  OFF

/*--------------------------PORT Define----------------------------*/
/*---SPI---*/
#define SBC4500_MOSI_Port 	 Bsw_Port_B
#define SBC4500_MOSI_Pin 	 4

#define SBC4500_MISO_Port 	 Bsw_Port_B
#define SBC4500_MISO_Pin 	 3

#define SBC4500_SCLK_Port 	 Bsw_Port_B
#define SBC4500_SCLK_Pin 	 2

#define SBC4500_NCS_Port 	 Bsw_Port_B
#define SBC4500_NCS_Pin 	 5

/*---SBC中断---*/
#define SBC4500_INTB_Port 	 Bsw_Port_D
#define SBC4500_INTB_Pin 	 6

/*---Fail Safe---*/
#define SBC4500_FS0B_Port
#define SBC4500_FS0B_Pin

#define SBC4500_FS1B_Port
#define SBC4500_FS1B_Pin

#define SBC4500_IO_2_Port	Bsw_Port_A  //FCCU
#define SBC4500_IO_2_Pin	12



/*---ADC---*/
#define SBC4500_MUX_OUT_Port
#define SBC4500_MUX_OUT_Pin

#define SBC4500_VDDIO_Port
#define SBC4500_VDDIO_Pin

/*------------------------------------------------------------------*/
/**************************************************************************************************************************************************
 * 																    	 ||
 *MOSI:	bit51	bit14	bit13	bit12	bit11	bit10	bit9	bit8 	 ||	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
 * 		R/W		M/FS	A4		A3		A2		A1		A0		P		 ||	D7		D6		D5		D4		D3		D2		D1		D0
 *MISO:	bit51	bit14	bit13	bit12	bit11	bit10	bit9	bit8	 ||	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
 * 		SPI_G	WU_G	CAN_G	LIN_G	IO_G	VPRE_G	VCORE_G	VOTHERS_G||
 * 				bit15:8 always sent by Main digital						 ||Extended diagnosis:sent by Main or Fail Safe based on bits 15:9 MOSI
 *
 **************************************************************************************************************************************************
 */
/*------------------------Parity_bit way------------------------------------*/
#define SBC_Parity_odd  0
#define SBC_Parity_even	1

#define Parity_bit	SBC_Parity_odd

/*------------------------Register mapping---------------------------*/
/*------main logic------*/
#define SBC_INIT_VREG  			(1U)	/*Write during INIT phase then read only*/
#define SBC_INIT_WU1			(2U)	/*Write during INIT phase then read only*/
#define SBC_INIT_WU2			(3U)	/*Write during INIT phase then read only*/
#define	SBC_INIT_INT			(4U)	/*Write during INIT phase then read only*/
#define SBC_INIT_INH_INT		(5U)	/*Write during INIT phase then read only*/
#define SBC_LONG_DURATION_TIMER	(6U)	/*Write during INIT phase then read only*/
#define SBC_HW_CONFIG			(8U)	/*Read only*/
#define	SBC_WU_SOURCE			(9U)	/*Read only*/
#define	SBC_DEVICE_ID			(10U)	/*Read only*/
#define	SBC_IO_INPUT			(11U)	/*Read only*/
#define	SBC_DIAG_VPRE			(12U)	/*Read only*/
#define	SBC_DIAG_VCORE			(13U)	/*Read only*/
#define	SBC_DIAG_VCCA			(14U)	/*Read only*/
#define	SBC_DIAG_VAUX			(15U)	/*Read only*/
#define	SBC_DIAG_VSUP_VCAN		(16U)	/*Read only*/
#define	SBC_DIAG_CAN_FD			(17U)	/*Read only*/
#define	SBC_DIAG_CAN_LIN		(18U)	/*Read only*/
#define	SBC_DIAG_SPI			(19U)	/*Read only*/
#define	SBC_MODE				(21U)	/*Write during normal and read*/
#define	SBC_REG_MODE			(22U)	/*Write during normal and read*/
#define	SBC_IO_OUT_AMUX			(23U)	/*Write during normal and read*/
#define	SBC_CAN_LIN_MODE		(24U)	/*Write during normal and read*/
#define	SBC_LDT_AFTER_RUN_1		(26U)	/*Write during normal and read*/
#define	SBC_LDT_AFTER_RUN_2		(27U)	/*Write during normal and read*/
#define	SBC_LDT_WAKE_UP_1		(28U)	/*Write during normal and read*/
#define	SBC_LDT_WAKE_UP_2		(29U)	/*Write during normal and read*/
#define	SBC_LDT_WAKE_UP_3		(30U)	/*Write during normal and read*/

/*------fail-safe logic-----*/
#define	SBC_INIT_FS1B_TIMING		(33U)	/*Write during INIT phase then read only*/
#define	SBC_BIST					(34U)	/*Write (No restriction) and read*/
#define	SBC_INIT_SUPERVISOR			(35U)	/*Write during INIT phase then read only*/
#define	SBC_INIT_FAULT				(36U)	/*Write during INIT phase then read only*/
#define	SBC_INIT_FSSM				(37U)	/*Write during INIT phase then read only*/
#define	SBC_INIT_SF_IMPACT			(38U)	/*Write during INIT phase then read only*/
#define	SBC_WD_WINDOW				(39U)	/*Write (No restriction) and read*/
#define	SBC_WD_LFSR					(40U)	/*Write (No restriction) and read*/
#define	SBC_WD_ANSWER				(41U)	/*Write (No restriction) and read*/
#define	SBC_RELEASE_FSxB			(42U)	/*Write (No restriction) and read*/
#define	SBC_SF_OUTPUT_REQUEST		(43U)	/*Write (No restriction) and read*/
#define	SBC_INIT_WD_CNT				(44U)	/*Write during INIT phase then read only*/
#define	SBC_DIAG_SF_IOs				(45U)	/*Read only*/
#define	SBC_WD_COUNTER				(46U)	/*Read only*/
#define	SBC_DIAG_SF_ERR				(47U)	/*Read only*/
#define	SBC_INIT_VCORE_OVUV_IMPACT	(49U)	/*Write during INIT phase then read only*/
#define	SBC_INIT_VCCA_OVUV_IMPACT	(50U)	/*Write during INIT phase then read only*/
#define	SBC_INIT_VAUX_OVUV_IMPACT	(51U)	/*Write during INIT phase then read only*/
#define	SBC_DEVICE_ID_FS			(52U)	/*Read only*/



/*-------------------------------- Data type definition-----------------------------------*/

typedef enum
{
	Common,
	Secure
}SBC_SecureTpye;


typedef  struct
{
	SBC_SecureTpye SecureTpye;
    union
    {
		uint8_t  DataFld;     /* bit 0 .. 7                 */
        struct
        {
			uint8_t	bit0 	: 1;
			uint8_t	bit1   	: 1;
			uint8_t	bit2 	: 1;
			uint8_t	bit3	: 1;
			uint8_t	bit4   	: 1;
			uint8_t	bit5	: 1;
			uint8_t	bit6	: 1;
			uint8_t	bit7	: 1;
        }Bits;
    }Command;
}CommandType;



#if 0
/*-------------------------------- Write Command definition-----------------------------------*/
/*---------Main logic register-------*/
CommandTypess SBC_INIT_VREG_Command = 	/* bit7: ICCA_LIM		0: ICCA_LIM_OUT 		       					*/
{										/* bit6: TCCA_LIM_OFF	1: 50ms        		 		 					*/
	Common,								/* bit5: IPFF_DIS		0: Enabled					 					*/
	{									/* bit4: VCAN_OV_MON	1: On					     					*/
			0x54						/* bit3:           		0												*/
	}									/* bit2: TAUX_LIM_OFF	1: 50ms 				 					    */
										/* bit1: VAUX_TRK_EN	0: NO tracking			            			*/
};										/* bit0:          		0        										*/

CommandType SBC_INIT_WU1_Command =		/* bit7-6: WU_IO0 		01: Wake-up on rising edge - or high level	KL15*/
{										/* bit5-4: WU_IO2		00: NO wake-up capability						*/
	Common,								/* bit3-2: WU_IO3		01: Wake-up on rising edge - or high level	CAN	*/
	{									/* bit3-2: WU_IO4		01: Wake-up on rising edge - or high level	RTC	*/
			0x45
	}

};

CommandType SBC_INIT_WU2_Command =		/* bit7-6: WU_IO5 		01: Wake-up on rising edge - or high level			33771*/
{										/* bit5: CAN_DIS_CFG 	 0: CAN in Rx only mode						FS1B Not Used*/
	Common,								/* bit4: CAN_WU_TO 		 0: 120μs										Not Used */
	{									/* bit3:           		 0														 */
			0x40						/* bit2: LIN_J2602_dis   0: Compliant with J2602 standard(Default)		Not Used */
	}									/* bit1-0: LIN_SR_1:0   00: 20 kbits/s									Not Used */

};

CommandType SBC_INIT_INT_Command =		/* bit7: INT_DURATION 		0: 100μs											*/
{										/* bit6: INT_INH_LIN 		1: LIN error bits change INHIBITED			Not Used*/
	Common,								/* bit5: INT_INH_ALL 		0: All INT sources									*/
	{									/* bit4: INT_INH_VSNS 		0: All INT sources							 		*/
			0x40						/* bit3: INT_INH_VPRE 		0: All INT sources							 		*/
	}									/* bit2: INT_INH_VCORE 		0: All INT sources							 		*/
										/* bit1: INT_INH_VOTHER 	0: All INT sources							 		*/
};										/* bit0: INT_INH_CAN 		0: All INT sources							 		*/

CommandType SBC_INIT_INH_INT_Command =	/* bit7-5:           		000:												 */
{										/* bit4:INT_INH_5           0:INT not masked									 */
	Common,								/* bit3:INT_INH_4 	        0:INT not masked									 */
	{									/* bit2:INT_INH_3           1:INT masked										 */
			0x06						/* bit1:INT_INH_2           1:INT masked										 */
	}									/* bit0:INT_INH_0           0:INT not masked									 */

};

CommandType SBC_LONG_DURATION_TIMER_Command =	/* bit7-5: F2:F0           100:Function 5										 */
{												/* bit4: REG_SE           	 0:Read programmed wake-up register					 */
	Common,										/* bit3:            	 	 0:													 */
	{											/* bit2: MODE           	 1:Normal mode (1 s resolution)						 */
			0x04								/* bit1: LDT_ENABLE          1:LDT counter Start									 */
	}											/* bit0: 			         0:													 */

};

CommandType SBC_MODE_Command =			/* bit7: VKAM_EN          		 0:DISABLED								 		*/
{										/* bit6: LPOFF_AUTO_WU           0:No action								 	*/
	Secure,								/* bit5: GO_LPOFF          		 0:No action								 	*/
	{									/* bit4: INT_REQ          		 0:No Request								 	*/
			0x00						/* bit3-0: Secure3-0          0000								 				*/
	}

};

CommandType SBC_REG_MODE_Command =		/* bit7: VCORE_EN          		 1:Enabled								 		*/
{										/* bit6: VCCA_EN          		 1:Enabled								 		*/
	Secure,								/* bit5: VAUX_EN          		 1:Enabled								 		*/
	{									/* bit4: VAUX_EN          		 1:Enabled								 		*/
			0xF0						/* bit3-0: Secure3-0          0000								 				*/
	}

};

CommandType SBC_IO_OUT_AMUX_Command =	/* bit7: IO_OUT_4_EN          	 0:High-impedance (IO_4 configured as input)	*/
{										/* bit6: IO_OUT_4          		 0:Low(Default)									*/
	Common,								/* bit5-3:         			   000								 				*/
	{									/* bit2-0:         			   000:VREF						 					*/
			0x00
	}

};

CommandType SBC_CAN_LIN_MODE_Command =	/* bit7-6: CAN_MODE_1:0         11:Normal operation mode 						*/
{										/* bit5: CAN_AUTO_DIS          	 1:Reset CAN_mode from ’11’ to ’01’ 			*/
	Common,								/* bit4-3: LIN_MODE_1:0         10:(Default)			 				Not Used*/
	{									/* bit2: LIN_AUTO_DIS         	 1:(Default)			 				Not Used*/
			0xF4						/* bit1-0:          	 		00						 				Not Used*/
	}

};

CommandType SBC_LDT_AFTER_RUN_1_Command =	/* bit7-0: B15:8      0:After run value (8 most significant bits) (Default)*/
{
	Common,
	{
			0x00
	}

};

CommandType SBC_LDT_AFTER_RUN_2_Command =	/* bit7-0: B7:0      0:After run value (8 least significant bits) (Default)*/
{
	Common,
	{
			0x00
	}

};

CommandType SBC_LDT_WAKE_UP_1_Command =		/* bit7-0: B23:16      0:Wake-up value (8 most significant bits) (Default)*/
{
	Common,
	{
			0x00
	}

};

CommandType SBC_LDT_WAKE_UP_2_Command =		/* bit7-0: B15:8      0:Wake-up value (8 intermediate bits) (Default)	*/
{
	Common,
	{
			0x00
	}

};

CommandType SBC_LDT_WAKE_UP_3_Command =		/* bit7-0: B7:0      0:Wake-up value (8 least significant bits) (Default)*/
{
	Common,
	{
			0x00
	}

};

/*---------Fail-safe logic register-------*/

CommandType SBC_INIT_FS1B_TIMING_Command =	/* bit7-4: FS1B_TIME_3:0     0110:37ms  					 (Default)*/
{											/* bit3-0: Secure3:0	     0000:		  					 (Default)*/
	Secure,
	{
			0x60
	}

};

CommandType SBC_BIST_Command =		/* bit7: 		    			0:		  					 		*/
{									/* bit6:ABIST2_FS1B    			1:Launch ABIST on FS1B		  		*/
	Secure,							/* bit5:ABIST2_VAUX    			1:Launch ABIST on VAUX	  			*/
									/* bit4: 		    			0:		  					 		*/
	{								/* bit3-0: Secure3:0	     0000:		  				   (Default)*/
			0x60
	}

};

CommandType SBC_INIT_SUPERVISOR_Command =	/* bit7:VCORE_5D    			0:detection threshold (VCORE_FB_UV) 		*/
{											/* bit6:VCCA_5D	    			0:detection threshold (VCCA_UV_5) 			*/
	Secure,									/* bit5:VAUX_5D	    			0:detection threshold (VAUX_UV_5) 			*/
	{										/* bit4:FS1B_TIME_RANGE	    	0:x1 timing range factor		 			*/
			0x00							/* bit3-0: Secure3:0	     0000:		  				   		   (Default)*/
	}

};

CommandType SBC_INIT_FAULT_Command =		/* bit7:FLT_ERR_FS    		0:intermediate = 3; final = 6		 						*/
{											/* bit6:FS1B_CAN_IMPACT		1:CAN in Rx only or sleep mode when FS1B is asserted 		*/
	Secure,									/* bit5-4:FLT_ERR_IMP_1:0  01:FS0B is asserted low if FLT_ERR_CNT ≥ intermediate value  */
	{										/* bit3-0: Secure3:0	 0000:		  				   		 				   (Default)*/
			0x50
	}

};

CommandType SBC_INIT_FSSM_Command =		/* bit7:IO_45_FS    		0:Not safety		 						*/
{										/* bit6:IO_23_FS    		1:Safety critical		 		   (Default)*/
	Secure,								/* bit5:PS    				0:Fccu_eaout_1:0 active high	   (Default)*/
	{									/* bit4:RSTB_DURATION		0:10ms							   (Default)*/
			0x40						/* bit3-0: Secure3:0	 0000:		  				   		   (Default)*/
	}

};

CommandType SBC_INIT_SF_IMPACT_Command =	/* bit7:TDLY_TDUR    		0:FS1B tDELAY mode		 			(Default)*/
{											/* bit6:DIS_8S    			0:Enabled		 					(Default)*/
	Secure,									/* bit5-4:WD_IMPACT_1:0    01:RSTB only is asserted low if WD error counter = WD_CNT_ERR[1:0]	(Default)*/
	{										/* bit3-0: Secure3:0	 0000:		  				   		   (Default)*/
			0x10
	}

};

CommandType SBC_WD_WINDOW_Command =		/* bit7-4: WD_WINDOW_3:0	 1101:		  	256ms			   		   		*/
{										/* bit3-0: Secure3:0	 	 0000:		  				   		   (Default)*/
	Secure,
	{
			0xD0
	}

};

CommandType SBC_WD_LFSR_Command =		/* bit7-0: WD_LFSR_7:0		 1011 0010:		  	0xB2			   (Default) */
{
	Common,
	{
			0xB2
	}

};

CommandType SBC_WD_ANSWER_Command =		/* bit7-0: WD_ANSWER_7:0		 0000 0000:		  	0x00			   (Default) */
{
	Common,
	{
			0x00
	}

};

CommandType SBC_RELEASE_FSxB_Command =	/* bit7-0: RELEASE_FSxB_7:0		 0000 0000:		  	0x00			   (Default) */
{
	Common,
	{
			0x00
	}

};

CommandType SBC_SF_OUTPUT_REQUEST_Command =		/* bit7: FS1B_REQ			 0:No request				  		  (Default)*/
{												/* bit6: FS1B_DLY_REQ		 1:open S1						   	 		   */
	Secure,										/* bit5: FS0B_REQ		 	 0:No request					   	 		   */
	{											/* bit4: RSTB_REQ		 	 0:No request					   	 		   */
			0x00								/* bit3-0: Secure3:0	  0000:		  				   		   	  (Default)*/
	}

};

CommandType SBC_INIT_WD_CNT_Command =		/* bit7-6: WD_CNT_ERR_1:0		00:6				  				  (Default)*/
{											/* bit5-4: WD_CNT_RFR_1:0		00:6				  				  (Default)*/
	Secure,									/* bit3-0: Secure3:0	      0000:		  				   		   	  (Default)*/
	{
			0x00
	}

};

CommandType SBC_INIT_VCORE_OVUV_IMPACT_Command =	/* bit7-6: VCORE_FS_OV_1:0	11:VCORE_FB_OV does have an impact on RSTB and FS0B	  (Default)*/
{													/* bit5-4: VCORE_FS_UV_1:0	10:VCORE_FB_UV does have an impact on FS0B only	  	  (Default)*/
	Secure,											/* bit3-0: Secure3:0	  0000:		  				   		   					  (Default)*/
	{
			0xE0
	}

};

CommandType SBC_INIT_VCCA_OVUV_IMPACT_Command =		/* bit7-6: VCCA_FS_OV_1:0	11:VCCA_OV does have an impact on RSTB and FS0B	 	 (Default)*/
{													/* bit5-4: VCCA_FS_UV_1:0	10:VCCA_UV does have an impact on FS0B only	  	 	 (Default)*/
	Secure,											/* bit3-0: Secure3:0	  0000:		  				   		   					 (Default)*/
	{
			0xE0
	}

};

CommandType SBC_INIT_VAUX_OVUV_IMPACT_Command =		/* bit7-6: VAUX_FS_OV_1:0	11:VAUX_OV does have an impact on RSTB and FS0B	 	 (Default)*/
{													/* bit5-4: VAUX_FS_UV_1:0	10:VAUX_UV does have an impact on FS0B only	  	 	 (Default)*/
	Secure,											/* bit3-0: Secure3:0	  0000:		  				   		   					 (Default)*/
	{
			0xE0
	}

};


#endif


#endif /* ECU_SBC4500_H_ */
